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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
March 2009
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FOD8001 High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Features
High Noise Immunity characterized by Common Mode
Description
The FOD8001 is a 3.3V/5V high-speed logic gate Optocoupler, which supports isolated communications allowing digital signals to communicate between systems without conducting ground loops or hazardous voltages. It utilizes Fairchild's patented coplanar packaging technology, Optoplanar(R), and optimized IC design to achieve high noise immunity, characterized by high common mode rejection and power supply rejection specifications. This high-speed logic gate optocoupler, packaged in a compact 8-pin small outline package, consists of a highspeed AlGaAs LED driven by a CMOS buffer IC coupled to a CMOS detector IC. The detector IC comprises an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled to the high efficiency of the LED achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion).
Rejection (CMR) and Power Supply Rejection (PSR) specifications - 20kV/s Minimum Static CMR @ Vcm = 1000V - 25kV/s Typical Dynamic CMR @ Vcm = 1500V, 20MBaud Rate - PSR in excess of 10% of the supply voltages across full operating bandwidth High Speed: - 25Mbit/sec Date Rate (NRZ) - 40ns max. Propagation Delay - 6ns max. Pulse Width Distortion - 20ns max. Propagation Delay Skew 3.3V and 5V CMOS Compatibility
Extended industrial temperate range, -40C to 105C
temperature range
Safety and regulatory pending approvals:
- UL1577, 3750 VACRMS for 1 min. - IEC60747-5-2 (pending)
Related Resources
www.fairchildsemi.com/products/opto/ www.fairchildsemi.com/pf/FO/FOD0721.html www.fairchildsemi.com/pf/FO/FOD0720.html www.fairchildsemi.com/pf/FO/FOD0710.html
Applications
Industrial fieldbus communications
- Profibus, DeviceNet, CAN, RS485 Programmable Logic Control Isolated Data Acquisition System
Functional Schematic
VDD1 1 VI 2
8 VDD2 7 NC 6 VO 5 GND2 Truth Table VI LED H OFF L ON
*
3
VO H L
GND1 4
*: Pin 3 must be left unconnected
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
www.fairchildsemi.com
FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Pin Definitions
Pin Number
1 2
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Pin Name
VDD1 VI GND1 GND2 VO NC VDD2 Input Supply Voltage Input Data
Pin Function Description
3 4 5 6 7 8
LED Anode - Must be left unconnected Input Ground Output Ground Output Data Not Connected Output Supply Voltage
Absolute Maximum Ratings (TA = 25C Unless otherwise specified.) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
TSTG TOPR TSOL VDD1, VDD2 VI II VO IO PDI PDO
Parameter
Storage Temperature Operating Temperature Lead Solder Temperature (Refer to Reflow Temperature Profile) Supply Voltage Input Voltage Input DC Current Output Voltage Average Output Current Input Power Dissipation(1)(3) Total Power Dissipation(2)(3)
Value
-55 to +125 -40 to +105 260 for 10 sec 0 to 6.0 -0.5 to VDD1 + 0.5 -10 to +10 -0.5 to VDD2 + 0.5 10 90 70
Units
C C C V V A V mA mW mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
TA VDD1, VDD2 VIH VIL tr, tf
Parameter
Ambient Operating Temperature Supply Voltages (3.3V Operation)(4) Supply Voltages (5.0V Operation)(4) Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Time
Min.
-40 3.0 4.5 2.0 0
Max.
+105 3.6 5.5 VDD 0.8 1.0
Unit
C V V V ms
Notes: 1. Derate linearly from 25C at a rate of tbd W/C 2. Derate linearly from 25C at a rate of tbd mW/C. 3. Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected to conditions outside these ratings. 4. 0.1F bypass capacitor must be connected between Pin 1 and 4, and 5 and 8.
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2 www.fairchildsemi.com 2
FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Isolation Characteristics (Apply over all recommended conditions, typical value is measured at TA = 25C)
Symbol
VISO RISO
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Characteristics
Input-Output Isolation Voltage Isolation Resistance Isolation Capacitance VI-O =
Test Conditions
f = 60Hz, t = 1.0 min, II-O 500V(5) 1.0MHz(5) VI-O = 0V, f = 10A(5)(6)
Min.
3750 1011 --
Typ.* Max.
-- -- 0.2 -- -- --
Unit
VacRMS pF
C
Notes: 5. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 6. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration.
Electrical Characteristics (Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25C)
Symbol
IDD1L IDD1H IIA, IIB IDD2L IDD2H VOH
Parameter
Logic Low Input Supply Current Logic High Input Supply Current Input Current Logic Low Output Supply Current Logic High Output Supply Current Logic High Output Voltage VI = 0V VI = VDD1 VI = 0V VI = VDD1
Conditions
Min.
Typ.
6.2 0.8
Max.
10.0 3.0 +10
Units
mA mA A mA mA V
INPUT CHARACTERISTICS
-10 4.5 4.5 2.9 1.9 4.4 4.0 3.3 2.9 5.0 4.8 0 0.3
OUTPUT CHARACTERISTICS 9.0 9.0
IO = -20A, VI = VIH, VDD2 = +3.3V IO = -4mA, VI = VIH, VDD2 = +3.3V IO = -20A, VI = VIH, VDD2 = +5.0V IO = -4mA, VI = VIH, VDD2 = +5.0V
VOL
Logic Low Output Voltage
IO = 20A, VI = VIL IO = 4mA, VI = VIL
0.1 1.0
V
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Switching Characteristics (Apply over all recommended conditions, typical value is measured at
VDD1 = VDD2 = +3.3V, VDD1 = +3.3V and VDD2 = +5.0V, VDD1 = +5.0V and VDD2 = +3.3V, VDD1 = VDD2 = +5.0V, TA = 25C)
Symbol Parameter
tPHL
w w w . d
Test Conditions
CL = 15pF
Min.
Typ.
25 25 2
Max.
40 40 6 25
Unit
ns ns ns Mb/s ns ns ns kV/s kV/s pF pF
Propagation Delay Time to Logic Low Output
a asheet4u. m tPLH t Propagation Delay Time to c o CL = 15pF Logic High Output
PWD
Pulse Width Distortion, | tPHL - tPLH | Data Rate Propagation Delay Skew Output Rise Time (10%-90%) Output Fall Time (90%-10%) Common Mode Transient Immunity at Output High Common Mode Transient Immunity at Output Low Input Dynamic Power Dissipation Capacitance(9) Output Dynamic Power Dissipation Capacitance(9)
PWD = 40ns, CL = 15pF
tPSK tR tF |CMH| |CML| CPDI CPDO
CL = 15pF(7) 6.5 6.5 VI = VDD1, VO > 0.8 VDD1, VCM = 1000V(8) VI = 0V, VO < 0.8V, VCM = 1000V(8) 20 20 40 40 30 3
20
Notes: 7. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low. 9. Unloaded dynamic power dissipation is calculated as follows: CPD x VDD x f + IDD + VPD where f is switched time in MHz.
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Typical Performance Curves
Figure 1. Typical Output Voltage vs. Input Voltage
4.0 VDD1 = VDD2 = 3.3V
VITH - Typical Input Voltage Swicthing Threshold (V)
Figure 2. Input Voltage Switching Threshold vs. Input Supply Voltage
2.0 VDD2 = 3.3V
3.5
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VO - Output Voltage (V) 2.5
1.8
1.6
2.0
1.5
1.4
1.0
1.2
0.5
0.0 0 1 2 3 4 5 VI - Input Voltage (V)
1.0 3.0 3.5 4.0 4.5 5.0 5.5 VDD1 - Input Supply Voltage (V)
Figure 3. Propogation Delay vs. Ambient Temperature
32 4.0 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
Figure 4. Pulse Width Distortion vs. Ambient Temperature
Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
3.5
30 PWD - Pulse Width Distortion (ns) 3.0
t P - Propagation Delay (ns)
28
2.5
26 t
PHL
2.0
1.5
24
t
PLH
1.0
22 0.5
20 -40 -20 0 20 40 60 80 100 TA - Ambient Temperature (C)
0.0 -40 -20 0 20 40 60 TA - Ambient Temperature (C) 80 100
Figure 5. Typical Rise Time vs. Ambient Temperature
7.5 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
7.5
Figure 6. Typical Fall Time vs. Ambient Temperature
Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
7.0
7.0
6.5
t r - Rise Time (ns)
tf - Fall Time (ns)
6.0
6.5
5.5
6.0
5.0
4.5
5.5 -40 -20 0 20 40 60 80 100 TA - Ambient Temperature (C)
4.0 -40 -20 0 20 40 60 TA - Ambient Temperature (C) 80 100
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Typical Performance Curves (Continued)
Figure 7. Typical Propogation Delay vs. Output Load Capacitance
34 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V 32
Figure 8. Typical Width Distortion vs. Output Load Capacitance
2.6 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
2.4
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30
PWD - Pulse Width Distortion (ns) 2.2
t P - Propagation Delay (ns)
2.0
28
t
PHL
1.8
26
1.6
t
PLH
1.4
24
1.2
22 15 20 25 30 35 40 45 50 55 C L - Output Load Capacitance (pF)
1.0 15 20 25 30 35 40 45 50 55 C L - Output Load Capacitance (pF)
Figure 9. Typical Rise Time vs. Output Load Capacitance
12 16 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
Figure 10. Typical Fall Time vs. Output Load Capacitance
Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 3.3V
11
14
10
12 tf - Fall Time (ns)
tr - Rise Time (ns)
9
10
8
8
7
6 6 4
5
4 15 20 25 30 35 40 45 C L - Output Load Capacitance (pF) 50 55
2 15 20 25 30 35 40 45 50 55 C L - Output Load Capacitance (pF)
Figure 11. Input Supply Current vs. Frequency
6.5
6.0
Figure 12. Output Supply Current vs. Frequency
V DD1 = VDD2 = 5.5V * Pin 6 Floating
VDD1 = 5.5V
6.0
5.8 IDD2 - Output Supply Current (mA) T = 25C
A
IDD1 - Input Supply Current (mA)
5.5
T = 105C
A
5.6 TA = -40C
5.0
T = 25C
A
4.5
T = -40C
A
5.4
T = 105C
A
4.0
5.2
3.5
3.0 0 2000 4000 6000 8000 f - Frequency (kHz) 10000 12000
5.0 0 2000 4000 6000 8000 f - Frequency (kHz) 10000 12000
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Test Circuits
1 0.1F 2 7 0.1F VO CL 4 5 8
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DD1 = 3.3V
0V-3.3V 3 Pulse width = 40ns Duty Cycle = 50% 6
VDD2 = 3.3V
tPLH Input VIN
tPHL
3.3V 50%
Output
90%
VOH
50%
VOUT 10% tR tF
VOL
Figure 13. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
1 0.1F SW A VDD1 = 3.3V B 3 2
8 0.1F VDD2 = 3.3V VO CL
7
6
4
+ -
5
VCM
1kV GND VOH
Switching Pos. (A) VIN = 3.3V
VCM
CMH
0.8 x VDD
0.8V VOL
Switching Pos. (B) VIN = 0V
CML
Figure 14. Test Circuit for Instantaneous Common Mode Rejection Voltage
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Application Information
Noise is defined as any unwanted signal that degrades or interferes with the operation of a system or circuit. Input-output noise rejection is a key characteristic of an optocoupler, and the performance specification for this noise rejection is called, "Common Mode Transient www..com Immunity or Common Mode Rejection, CMR". The CMR test configuration is presented in high speed optocoupler datasheets, which tests the optocoupler to a specified rate of interfering signal (dv/dt), at a specified peak voltage (Vcm). This defined noise signal is applied to the test device while the coupler is a stable logic high or logic low state. This test procedure evaluates the interface device in a constant or static logic state. This type of CMR can be referred to as "Static CMR". Fairchild's high speed optocouplers, which use an optically transparent, electrically conductive shield, and offer active totem pole logic output have static CMR in excess of 50KV/us at peak amplitudes of 1.5kV to 2.0kV. Test circuit functions were built to interface a commercial pseudo-random bit sequence (PRBS) generator and error detector with a pair of high speed optocouplers, FOD8001, connected in a loop-back configuration. With a 10MBaud PRBS serial data stream, no error was detected until the common mode voltage rose above 2.5kV with a dv/dt of 45kV/us. And increasing the data rate beyond 10Mbaud, the test was conducted at 20MBaud, and no error was detected at dv/dt of 25kV/us at common mode voltage of 1.5kV. The test data for the dynamic CMR is comparable or better than the static CMR specifications found in the datasheet. These excellent noise rejection performances are results of the innovative circuit design and the patented coplanar assembly process.
Power Supply Noise Rejection
High levels of electrical noise can cause the optocoupler to register the incorrect logic state. The most commonly discussed noise signal is the common mode noise found between the input and output of the optocoupler. However, common mode noise is not the only path of noise into the input or output of the optocoupler. Due to the high gain and wide bandwidth of the transimpedance amplifier used for the photo detector circuits, power supply noise can cause the optocoupler to change state independent of the LED operation. Power supply noise is typically characterized as either random or periodic pulses with varying amplitudes and rates of rise and fall. The necessary tests have been conducted to understand the influence of the power supply noise and its effect of the proper operation of the FOD8001. The optocoupler under test offered power supply noise rejection in excess of 10% of the supply voltage for a frequency ranging from 100kHz to 35MHz, for logic high and logic low states.
Dynamic Common Mode Rejection
The noise susceptibility of an interface while it is actively transferring data is a common requirement in serial data communication. However, the static CMR specification is not adequate in quantifying the electrical noise susceptibility for optocouplers used in isolating high speed data transfer. A serial data communication network's noise performance is usually quantified as the number of bit errors per second or as a ratio of the number of bits transmitted in a specified time frame. This describes Bit Error Rate, BER. Test equipment that evaluates BER is called a Bit Error Rate Tester, BERT. When a BERT system is combined with a CMR tester, the active or dynamic noise rejection of an isolated interface can then be quantified. This type of CMR is thus defined as "Dynamic CMR". Therefore, evaluating the common mode rejection while the optocoupler is switching at high speed represents a realistic approach to understand noise interference.
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Small Outline Package Dimensions
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0.164 (4.16) 0.144 (3.66)
SEATING PLANE
0.202 (5.13) 0.182 (4.63)
0.143 (3.63) 0.123 (3.13)
0.010 (0.25) 0.006 (0.16)
0.021 (0.53) 0.011 (0.28)
0.008 (0.20) 0.003 (0.08) 0.050 (1.27) TYP
0.244 (6.19) 0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
0.024 (0.61)
0.060 (1.52) 0.275 (6.99) 0.155 (3.94)
0.050 (1.27)
Note: All dimensions are in millimeters.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Carrier Tape Specification
8.0 0.10 3.50 0.20 0.30 MAX 4.0 0.10 2.0 0.05 O1.5 MIN 1.75 0.10
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5.5 0.05 8.3 0.10 12.0 0.3 5.20 0.20
0.1 MAX
6.40 0.20
O1.5 0.1/-0
User Direction of Feed
Note: All dimensions are in millimeters.
Ordering Information
Option
No Suffix R2
Order Entry Identifier
FOD8001 FOD8001R2
Description
Small outline 8-pin, shipped in tubes (50 units per tube) Small outline 8-pin, tape and reel (2,500 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
8001 X YY S1
2
5
3
4
Definitions
1 2 3 4 5
Fairchild logo Device number One digit year code, e.g., `8' Two digit work week ranging from `01' to `53' Assembly package code
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
Reflow Profile
300 280 260 240 220 200 180 Temperature (C) 160 140 120 100 80 60 40 20 0 0 60 120 Time (s) 180 270 360 33 Sec 1.822C/Sec Ramp up rate Time above 183C = 90 Sec 260C >245C = 42 Sec
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(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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FOD8001 -- High Noise Immunity, 3.3V/5V Logic Gate Optocoupler
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Rev. I38
(c)2008 Fairchild Semiconductor Corporation FOD8001 Rev. 1.0.2
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